1. Field of the Invention
The present invention relates to very large scale integrated circuits comprising a plurality of selectably interconnectable data processing cells, where the cells are incorporated into the overall working of the integrated circuit dependently upon their having passed a test of their functionality. In particular, the present invention relates to such a circuit disposed over the surface of a semiconductor wafer substrate.
2. The Prior Art
It is known to form an integrated circuit over the entire surface of a semiconductor wafer substrate up to several inches in diameter, the circuit consisting in a plurality of cells in a tessellation across the wafer face. Each cell is selectably operable to receive and provide data coupling to one or more of its neighboring cells. Starting at a port, coupling is provided to a first cell or cells from the outside world. The first cell or cells are tested and coupling to the port is confirmed if the test is passed. Thereafter, the cells which have just passed the test are operable to couple to an as yet untested neighboring cell for it to be tested. If the new neighbors pass the test they too are incorporated into the operation of the circuit and in turn couple to other untested neighbors for the other neighbors to be tested. In this way cells are progressively tested across the surface of the wafer, incorporated into the overall operation of the circuit if they are found to be working and rejected and bypassed if they are found not to work. The inherent failure rate in the fabrication of the individual cells when making such a wafer is thereby helped by weeding out those that cannot operate.
Various methods exist for selecting which neighboring cells are to be tested.
In a first method, each cell has a direction counter. The direction counters in all of the cells are synchronized and moved by a globally-provided clock signal to all move together. Any cell which has previously been tested resists further testing. Each cell, as it is tested and, if passing the test, becomes incorporated, is enabled to couple to neighboring cells to initiate their testing. All incorporated cells attempt to couple in the current test direction to any neighbor which will accept the approach. The simultaneous coupling and testing from all incorporated cells results in a rapidly-growing branched-labyrinth of cells forming across the surface of the wafer.
In a second method each cell, once tested and incorporated, resists further testing and, as before, is enabled to couple to an untested neighbor for that neighor to be tested. The cell does not comprise a direction counter and is commanded from outside which neighbor it is to couple to. Only one cell at a time is tested on the whole wafer. A spiral of cells is formed from the port wherein each cell is coupled to from just one neighbor and provides further coupling to just one other neighbor.
In a third method, a spiral of cells is grown similarly to the second method, with the exception that, whereas in the second method, when a cell is found which has no neighbor which passes the test or which will accept a coupling approach, indicating that the growing tip of the spiral has found the end of a blind cul-de-sac, the growth retreats back down the cul-de-sac dis-incorporating each cell in turn until a cell is found having a neighbor from which growth can continue and leaving behind a non-incorporated body of known working cells in the cul-de-sac. In the third method, cells are not dis-incorporated in the retreat from a cul-de-sac and the cell which is eventually found having an incorporable neighbor is allowed to couple out both to the new neighbor from which growth will continue and to the cul-de-sac, the third method producing a branched-spiral of intercoupled cells across the surface of the wafer.
The three methods described provide only a representative sample of the numerous methods available.
The manner of coupling between cells is simplified if the data is allowed to circulate in a closed path within each cell unless that cell is coupled to from a neighbor, in which case, data which would otherwise have been circulated within the cell is passed to the neighbor across the appropriate boundary and data which would otherwise have circulated within the neighbor is passed across the same boundary to the cell. When the overall circuit is configured, a data processing loop is formed starting at and returning to the port. At each stage of growth the operation of cells can be checked by data being passed in at the port and compared with the data returning back from the loop to the port. The sequence of instructions required for testing is simplified and the amount of hardware in each cell is minimized.
It has been the practice to arrange that cells are rectangular or square each having four boundary-sharing neighbors and four data processing elements in each cell for processing data either passed round the cell or received from a neighbor, the processed data either being passed further round the cell to another data processing element in the cell or across the boundary to another neighbor.
Cells should be kept small in order to maximize the proportion of cells which are found to be working subsequently to the manufacture of the wafer. If the cells are kept small then the size of each data processing element is unacceptably reduced, whereas if the size of the cells is increased to make the data processing elements each acceptably large, then the percentage yield of working cells becomes too low.
It is sometimes important to have a foreknowledge of the delay between data processing elements. In those cases where the data processing elements in the cells do more than the simple storing or retrieval of data, for example, when the data processing elements in a plurality of cells collectively form a digital processor or similarly complicated apparatus, the parts of the apparatus being spaced among many cells, it becomes very important to be able to control and/or predict the delays encountered in the transfer of data between cells.
Accordingly it is desirable to provide an integrated circuit wherein the individual data processing elements are large enough for convenient use without any accompanying sacrifice of percentage working yield of operational cells in the integrated circuit. It is also desirable that the cells in the circuit are interconnectable according to a large variety of methods. It is yet further a desirable feature that the delay time for data passing between data processing elements is a predicatable quantity,